Layout Generation of Array Cell for NMOS 4-phase Dynamic Logic
نویسندگان
چکیده
| An array cell (AC) architecture for the layout design is described, which is dedicated to lowpower design by means of the NMOS 4-phase dynamic logic. An AC is constructed of (M N)+2 transistors so as to constitute each type of NMOS 4-phase logic gates. A graph theoretic approach is exploited in the layout design to reduce the layout area. A number of experimental results demonstrate the practicability of the proposed approach.
منابع مشابه
Optimized Standard Cell Generation for Static CMOS Technology
Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the design stage, an Euleri...
متن کاملOptimized Standard Cell Generation for Static CMOS Technology
Fabrication of an integrated circuit with smaller area, besides reducing the cost of manufacturing, usually causes a reduction in the power dissipation and propagation delay. Using the static CMOS technology to fabricate a circuit that realizes a specific logic function and occupies a minimum space, it must be implemented with continuous diffusion runs. Therefore, at the design stage, an Euleri...
متن کاملMultiple-Cell-Upset Tolerant 6T SRAM Using NMOS-Centered Cell Layout
This paper presents a proposed NMOS-centered 6T SRAM cell layout that reduces a neutron-induced multiple-cell-upset (MCU) SER on a same wordline. We implemented an 1-Mb SRAM macro in a 65-nm CMOS process and irradiated neutrons as a neutron-accelerated test to evaluate the MCU SER. The proposed 6T SRAM macro improves the horizontal MCU SER by 67–98% compared with a general macro that has PMOS-c...
متن کامل1983 - TALIB: An IC Layout Design Assistant
This paper describes a knowledge-based system for automatically synthesizing integrated circuit layouts for NMOS cells. The desired cell layouts are specified in terms of their general structural and functional characteristics. From these initial specifications, the system produces correct and CoriJpact cell layouts. The system performs this task by generating plan steps at different levels of ...
متن کاملOptimum Gate Ordering of CMOS Logic Gates using Euler Path Approach: Some Insights and Explanations
The paper addresses some insights into the Euler path approach to find out the optimum gate ordering of CMOS logic gates. Minimization of circuit layout area is one of the fundamental considerations in circuit layout synthesis. Euler path approach suggests that finding a common Euler path in both the NMOS and PMOS minimizes the logic gate layout area. In this article, the minimization of layout...
متن کامل